@booklet {kanev2013measuring,
	title = {Measuring Code Optimization Impact on Voltage Noise},
	journal = {Workshop on Silicon Errors in Logic - System Effects (SELSE)},
	year = {2013},
	abstract = {In this paper, we characterize the impact of compiler optimizations on voltage noise. While intuition may suggest that the better processor utilization ensured by optimizing compilers results in a small amount of voltage variation, our measurements on a IntelR CoreTM2 Duo processor show the opposite {\textendash} the majority of SPEC 2006 benchmarks exhibit more voltage droops when aggressively optimized. We show that this increase in noise could be sufficient for a net performance decrease in a typicalcase, resilient design.},
	author = {Svilen Kanev and Jones, Timothy M and Gu-Yeon Wei and Brooks, David M and Reddi, Vijay Janapa}
}
