@article {kanevsystem,
	title = {A System-Level View of Voltage Noise in Production Processors},
	journal = {ACM Transactions on Architecture and Code Optimization},
	volume = {9},
	number = {4},
	year = {2010},
	abstract = {
	Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is es- pecially daunting because it happens rapidly. We measure and characterize voltage variation in a running Intel⃝R\&nbsp;CoreTM2 Duo processor. By sensing on-die voltage as the processor runs single-threaded, multi- threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4\%, far from the processor{\textquoteright}s 14\% worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With the investigated processors, such\&nbsp;resilient\&nbsp;designs could yield 15\% to 20\% performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing microarchitectural activity that leads to voltage swings within multi-core systems, we show two software techniques that have the potential to mitigate such voltage emergencies. A voltage-aware compiler can choose to de-optimize for performance in favor of better noise behavior, while a thread scheduler can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.

},
	author = {Svilen Kanev and Reddi, Vijay Janapa and Timothy M. Jones and Kim, Wonyoung and Campanoni, Simone and Michael D. Smith and Gu-Yeon Wei and David Brooks}
}
