@conference {leng2015gpu,
	title = {Gpu Voltage Noise: Characterization and Hierarchical Smoothing of Spatial and Temporal Voltage Noise Interference in Gpu Architectures},
	booktitle = {21st International Symposium on High Performance Computer Architecture (HPCA)},
	year = {2015},
	pages = {161{\textendash}173},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Energy efficiency is undoubtedly important for GPU architectures. Besides the traditionally explored energy-efficiency optimization techniques, exploiting the supply voltage guardband remains a promising yet unexplored opportunity. Our hardware measurements show that up to 23\% of the nominal supply voltage can be eliminated to improve GPU energy efficiency by as much as 25\%. The key obstacle for exploiting this opportunity lies in understanding the characteristics and root causes of large voltage droops in GPU architectures and subsequently smoothing them away without severe performance penalties. The GPU{\textquoteright}s manycore nature complicates the voltage noise phenomenon, and its distinctive architecture features from the CPU necessitate a GPU-specific voltage noise analysis. In this paper, we make the following contributions. First, we provide a voltage noise categorization framework to identify, characterize, and understand voltage noise in the manycore GPU architecture. Second, we perform a microarchitecture-level voltage-droop root-cause analysis for the two major droop types we identify, namely the local first-order droop and the global second-order droop. Third, on the basis of our categorization and characterization, we propose a hierarchical voltage smoothing mechanism that mitigates each type of voltage droop. Our evaluation shows it can reduce up to 31\% worst-case droop, which translates to 11.8\% core-level and 7.8\% processor-level energy reduction},
	url = {https://doi.org/10.1109/HPCA.2015.7056030},
	author = {Leng, Jingwen and Zu, Yazhou and Reddi, Vijay Janapa}
}
