@article {9076808, title = {Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware Margins}, journal = {IEEE Transactions on Device and Materials Reliability}, volume = {20}, number = {2}, year = {2020}, month = {June}, pages = {341-350}, abstract = {Modern large-scale computing systems (data centers, supercomputers, cloud and edge setups and high-end cyber-physical systems) employ heterogeneous architectures that consist of multicore CPUs, general-purpose many-core GPUs, and programmable FPGAs. The effective utilization of these architectures poses several challenges, among which a primary one is power consumption. Voltage reduction is one of the most efficient methods to reduce power consumption of a chip. With the galloping adoption of hardware accelerators (i.e., GPUs and FPGAs) in large datacenters and other large-scale computing infrastructures, a comprehensive evaluation of the safe voltage reduction levels for each different chip can be employed for efficient reduction of the total power. We present a survey of recent studies in voltage margins reduction at the system level for modern CPUs, GPUs and FPGAs. The pessimistic voltage guardbands inserted by the silicon vendors can be exploited in all devices for significant power savings. On average, voltage reduction can reach 12\% in multicore CPUs, 20\% in manycore GPUs and 39\% in FPGAs.}, keywords = {6G mobile communication, accelerators, Artificial Intelligence, benchmark testing, comprehensive evaluation, conservative limits, data centers, energy efficiency, FAA, field programmable gate arrays, FPGA, galloping adoption, general-purpose many-core GPUs, Graphics processing units, hardware accelerators, heterogeneous architectures, Iron, large-scale computing infrastructures, many-core GPU, Materials reliability, modern CPUs, modern hardware margins, modern large-scale computing systems, multicore CPU, multicore CPUs, multiprocessing systems, pessimistic voltage guardbands, power consumption, power savings, programmable FPGAs, safe voltage reduction levels, system level, Three-dimensional displays, voltage margin reduction, Voltage margins, voltage margins reduction}, issn = {1558-2574}, doi = {10.1109/TDMR.2020.2989813}, author = {G. Papadimitriou and A. Chatzidimitriou and D. Gizopoulos and V. J. Reddi and J. Leng and B. Salami and O. S. Unsal and A. C. Kestelman} }