Software-Assisted Hardware Reliability: Abstracting Circuit-Level Challenges to the Software Stack

Citation:

V. J. Reddi, M. S. Gupta, M. D. Smith, G. - Y. Wei, D. Brooks, and S. Campanoni, “Software-Assisted Hardware Reliability: Abstracting Circuit-Level Challenges to the Software Stack,” in Proceedings of the 46th Annual Design Automation Conference, 2009, pp. 788–793.
Paper554 KB

Abstract:

Power constrained designs are becoming increasingly sensitive to supply voltage noise. We propose a hardware-software collaborative approach to enable aggressive operating margins: a checkpoint-recovery mechanism corrects margin violations, while a run-time software layer reschedules the program’s instruction stream to prevent recurring margin crossings at the same program location. The run-time layer removes 60% of these events with minimal overhead, thereby significantly improving overall performance.

Categories and Subject Descriptors

C.0 [Computer Systems Organization]: General— Hardware/Software interfaces and System architectures.

General Terms

Performance, Reliability.

Keywords

Runtime Optimization, Hardware Software Co-Design.

Publisher's Version

Last updated on 05/31/2019