Improving power/performance efficiency is critical for today’s processors. From edge devices to data centers, lower power or higher performance always produce better systems, measured by lower cost of ownership or longer battery time. Traditional processors rely on large "wasted" guardbands to handle rare cases, such as extreme di/dt effects, aging, temperature variation, etc. to guarantee reliable execution (as shown below). But such guardbands in the pipeline lead to wasted energy or poor performance. To mitigate these effects, Active Timing Margin (ATM) is the process of improving processor power/performance efficiency by dynamically optimizing the pipeline timing margin. ATM focuses on improving processor efficacy by adjusting the timing margin. ATM trims the pipeline timing margin with a control loop that adjusts voltage and frequency based on real-time chip environment monitoring.
To dynamically tune or adjust the timing margin there are numerous challenges. Hence, synergistic management from processor architecture design and system software scheduling is needed. To this end, our research investigates such things as the primary consumers of pipeline timing margin, including temperature, voltage, and process variation and how to best mitigate them in the processor through hardware and software co-design.