Power-constrained CMOS designs are making it increasingly difficult for microprocessor designers to cope with power supply noise. As current draw increases and operating voltage decreases, inductive noise threatens the robustness and limits the clock frequency of high-performance processors. Large current swings over small time scales cause large voltage swings in the power-delivery subsystem. A significant drop in supply voltage can cause timing margin violations by slowing logic circuits. For reliable operation of the processor, voltage emergencies - large voltage swings that violate noise margins - must be avoided.
Voltage variation on a simulated 4-core CPU system.
The traditional way to deal with inductive noise is to over-design the processor to tolerate worst-case fluctuations. Unfortunately, the gap between nominal and worst-case operating conditions in modern microprocessor designs is growing. Such conservative operating margins ensure robust operation of the system, but can severely degrade performance due to the lower operating frequencies. Hence, in our research to mitigate power supply noise, we explore a variety of hardware and software optimizations solutions. At the hardware level, we study means to predict and avoid the inductive noise droops altogether. At the software level, we do "voltage smoothing" across the chip by using compiler and operating system scheduling techniques. We also do co-design, coupling the hardware and software together to balance the noise reduction act collaboratively. Hardware can be fast and reactive, the software can be slow but proactive. Therefore, a combination of solutions often leads to the best solution. We use these techniques to cope with power supply noise in single- and multi-core CPUs, as well as many-core GPUs.